Large area matrices pose a particular problem which is that of the time required for reading the image recorded in the matrix: the matrix must be emptied row by row into a read register placed at the end of the columns of the matrix until all the rows have been emptied; but, between the unloading of one row of the matrix into the register and the unloading of the next row, the contents of the register must be read by emptying it stage by stage into a read circuit placed at the end of the register.
In order to obtain a high enough frame rate (for example, the typical frame rate of a video picture at 30 images per second), the read register must work at an extremely high rate and, at the same time, the column transfer phases must not take too long.
In order to improve its performance, it has already been proposed to divide the matrix, both horizontally and vertically, into two parts, hence into four quadrants, and to place an individual read register at the free end of the columns of each quadrant. There are therefore four read registers and the constraints on each register are the constraints corresponding to a matrix of reduced size.
Even when this disposition is used, it is not necessarily sufficient and accelerating the process of reading the image can be desirable.
The registers can also be provided with intermediate outputs instead of having a single output at the end of the register, but this results in additional topographical design constraints and multiplexing constraints for the different outputs of the registers.
The invention aims to propose a simple solution for the improvement of the read speed, which can furthermore be used in combination with the solutions that have just been presented (multiple registers and registers with multiple outputs).
In order to explain the invention, it is recalled that in a conventional image sensor:                the columns of the image capture matrix are each organized into column charge transfer registers for progressively shifting the charges of an image dot from one row to another within each column, each stage of the column register corresponding to an image dot;        each stage of the column register comprises several electrodes (typically four electrodes for a conventional matrix); the column charge transfer from one stage to the next, together with the transfer of the last row towards the read register, is performed over several successive clock pulses from a vertical scan timing clock; the clock pulses correspond to control signals for the various electrodes of the stage, in synchronization for the electrodes of same rank of all the rows of the matrix;        between the last row of dots of the image capture matrix and the read register situated at the end of the matrix columns, there is a transfer electrode that is controlled synchronously with the column transfer, in order to unload the charges from the last row into the read register at the same time as the charges advance from one row to the next in the rest of the matrix;        between two successive column charge transfers, time is allowed for successively emptying all the stages of the read register along a row, under the control of a horizontal scan timing clock; the frequency of the horizontal scan timing clock, for the transfer along a row, is much higher than the frequency of the vertical scan timing clock used for the column transfer.        
The scan rates, both horizontal and vertical, cannot exceed certain values which are dictated by the stray capacitances and resistances of the electrodes and by the power of the amplifiers that switch, between a high level and a low level, the potentials applied to the electrodes. The read register control signals, timed at the horizontal scan rate, drive very small electrodes (those of the horizontal register) so the scan speed can be high. But the vertical scan timing clock is much slower owing to the fact that amplifiers need to simultaneously drive N electrodes (for N rows of the matrix) whose stray resistances and capacitances are large since each of these N electrodes occupies the whole width of the matrix.
FIG. 1 shows, in a simplified form, a conventional read-cycle timing diagram for an image capture matrix whose columns are arranged in a transfer register with four electrodes per row, and in which the transfer of the charges from one row of dots to the next uses ten pulses of a vertical scan timing clock of elementary period T0. A transfer over ten pulses is conventional for registers with four electrodes per stage operating in MPP (multi-pinned phase) mode. Other modes are possible that use a variable number of electrodes and a variable number of clock pulses to advance the column charge transfer by one row.
The first line of the timing diagram shows the pulses from the vertical scan timing clock, whose period is T0. The four following lines show the control signals phi1, phi2, phi3, phi4 of the four successive electrodes of a matrix row. All the electrodes of same rank of the various rows are controlled by the same signals, in other words the first electrode (rank 1) of any row is controlled by the signal phi1, the second electrode (rank 2) of any row is controlled by the signal phi2, and the same for the signals phi3 and phi4 which control all the third electrodes and all the fourth electrodes, respectively.
The sixth line of the timing diagram shows the control of an electrode, called the transfer electrode, situated between the last row of dots of the matrix and the horizontal read register. This transfer electrode is controlled by a control signal phiTR for periodically lowering, synchronously with the vertical shift of the charges from one row to another, a potential barrier created by this electrode between the columns and the read register; this lowering of the barrier causes the charges to be unloaded from the last row into the register, after which the potential barrier is raised again by the end of the pulse phiTR (falling to the low level) for the whole time that the horizontal transfer of the read register will last. The signal phiTR is generally the same as phi1.
The seventh line of the timing diagram shows the horizontal scan timing pulses, of period TL much shorter than T0 since the read register can perform a charge transfer along a row much faster than the column charge transfer. For a matrix of 1000 rows and 1000 columns, these periods are of the order of 2 microseconds for T0 and 25 nanoseconds for TL, which is not adhered to in FIG. 1.
The eighth and ninth lines of the timing diagram show symbolically the two signals phiL1 and phiL2 for controlling the horizontal register (conventionally a two-phase register with two electrodes per stage of the register); the switching of these signals is timed by the clock with period TL; the signals phiL1 and phiL2 are interrupted during the whole vertical transfer phase of a row, which lasts around 20 microseconds in this example; subsequently; they are subsequently restored for a new horizontal transfer.
It will therefore be understood that, on the one hand, the horizontal transfer signals phiL1 and phiL2 are activated K times, for emptying the horizontal register, if there are K columns to be read in the matrix (corresponding to K stages of the horizontal read register); then, a succession of pulses phi1, phi2, phi3, phi4, phiTR, such as is shown in FIG. 1, is established in order to transfer a new row of the matrix into the read register; then, the read register is emptied by K activations of the signals phiL1 and phiL2.
This process is repeated N times if there are N rows in the matrix. At the end, the matrix will have been completely read and a new image reception can take place.